The present invention relates in general to circuits for generating and controlling computer clocks and in particular to circuits used to convert digital signals to an analog signal by integrating a current in a capacitor.
Phase-locked loops (PLL""s) have been widely used in high-speed communication systems because PLL""s efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency.
The phase/frequency detector (PFD) in a phase lock loop generates an error signal when the phase of the reference clock (RCLK) leads or lags the feedback clock (FBCLK) regardless of whether the phase difference is due to simply phase differences or phase and frequency differences. Because PLLs typically generate digital signals, the phase error signals switch between two logic states and the time the phase error signals remain at a logic level is indicative of relative lead or lag phase error. Typically, two signals are generated UP (when the phase error is a lag) and DOWN (when the phase error is a lead). These digital phase error signals are then applied to a circuit that is able to generate an analog control voltage for a voltage-controlled oscillator (VCO) to control the frequency of the VCO""s output. This VCO output is then fed back through a feedback circuit as the FBCLK.
A charge pump circuit is used in many PLLs to generate the analog control voltage for the VCO. The charge pump uses charge and discharge current sources to integrate the digital phase error signals to generate the analog control voltage. In a scalable system employing a PLL that may be operated in multiple distinct frequency ranges, it is desirable to have a charge pump that also has selectable operation ranges by modifying the current levels of the current sources. If the current ranges are sufficiently different, this may dictate two distinct current sources with different device sizes.
There is, therefore, a need for a dual mode charge pump circuit that allows for the selection of two operation ranges without resorting to separate current sources with different device sizes. This will conserve chip area and simplify circuit design.
A charge pump has two current sources with a positive source voltage and two current xe2x80x9csinksxe2x80x9d (current sources with a ground source voltage). A first current source is connected to a first charge pump node with a first electronic switch controlled by a first control signal and a first current sink is connected to the first charge pump node with a second electronic switch controlled by a second control signal. Likewise, a second current source is connected to a second charge pump node with a third electronic switch controlled by a third control signal and a second current sink is connected to the second charge pump node with a fourth electronic switch controlled by a fourth control signal. The outputs of the first and second current sources are connected with a first bi-directional electronic switch controlled by a mode control signal and the outputs of the first and second current sinks are connected with a second bi-directional electronic switch controlled by the mode control signal. The first and fourth control signals are logic complements and mutually exclusive with the second and third control signals which are also logic complements. The mode control signal is set to a logic one state to generate a first current level and a logic zero to set a second current level for components coupled from said first and second charge pump nodes to the ground source voltage.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.